Curriculum Vitae

name Bernd Paysan my photo
date of birth 1970/03/03
nationality German


1976-1978 Primary School [html]Neubiberg near Munich
1978-1980 Primary School [html]Samberger Schule in Munich
1980-1989 Abitur [html]Gymnasium in Pullach/Munich
1990-1997 Diplom Computer Science at [html]TU München

Alternative Civilian Service

1989-1990 alternative civilian service in [php]Martha-Maria hospital in Munich

Employment History

Date Employer & Role
2011/12-now [html]net2o secure communication My own startup to develop a next generation protocol stack, and uses the technology developed there to support customers that have various projects. See project net2o below for a bit more details.
Customer Project example: Customer Nova Welt Innovation (Hong Kong), visualize CAN bus protocol for charging electric vehicles: state transitions, error flags and voltage/current plot; record and play back stored log files.
2010/2-2011/9 [html]Dialog aquired power management design team
Senior Design Engineer:
  • Gasgauge: Firmware development: rewrote smart battery firmware algorithm to b16. Adapted algorithm for battery aging.
    Concept for fast battery characterization.
    Software: Debugger GUI and demonstration/data logging GUI, characterization data evaluation, validation tools.
    Digital design: integration into test chip.
2008/7-2010/2 [html]Diodes aquired Zetex PLC
IC Design Engineer:
  • Gasgauge: Digital design: Integration of b16 CPU, I²C interface, RAM, ROM, SPI for debugging, work on 10 bit ADC, debugger interface for software development and demonstration GUI (1 year)
  • Charger: Intersil 9221/Maxim 8601 clone, analog design: Comparator blocks, power transistors (including layout and device engineering), architecture, and voltage mode regulator (1 year)

Administration of the Munich Linux network
2005/4-2008/7 Zetex aquired Mikron AG
IC Design Engineer:
  • Direct digital feedback amplifier ([html]DDFA): Project leader of the modulator part. Digital design of I²S input, equalizer DSP, upsampling DSP, volume control; conversion from FPGA tool-based output stage. Delay-chain based high-speed ADC (>100MHz for 8 bits). Implementation of a GUI to operate the device and design filters. Verifying the operation and adding multi-channel mode to the Linux kernel driver for the I²S hardware on a blackfin board (3 years).

Administration of the Munich Linux network
1998/10-2005/4 Mikron AG
IC Design Engineer:
  • Smart Battery Fuel Gauge, third generation: Developed software simulator to develop and debug firmware, participated in firmware development, debugging and prototype evaluation (1 year)
  • Smart Battery Charger: Software simulator and firmware development, participated in SMBus interface development (half a year), redesign of digital part (new timer and watchdog, debugged SMBus) for second release (1/2 year)
  • Smart Battery Fuel Gauge, fourth generation: Software simulator, technical project leader. Integration and debugging of digital part, evaluation and test development (1.5 years).
  • Acoustic Touch Screen Controller (IntelliTouch): Project leader, digital design (integration of Inventra USB with AMBA bus and 8051, flash and SRAM), specification, analog supervision (analog part comprises two PLLs, amplification, bandpass filter, pipelined ADC) (2 years).
  • Laser barcode reader: Project leader, digital design (integration of b16, RAM, ROM, and SPI interface) (2 years, continued at Zetex)

From 2005 also administration of the Unix/Linux network
1997/7-1998/10 [html]Mixed Mode ASIC Design
ASIC Designer: consulting customers in ASIC projects. Wrote a C++ Model for a CAN peripheral for Siemens HL. Wrote tests for the VHDL model of the CAN peripheral.
Designed a generic peripheral class, support for event driven C++ hardware simulation library.
1990/1-now Own company
Software engineer: development of Forth systems, Forth GUIs, part-time job, see projects below



German (mother tong), English (excellent), French (fluent), Chinese (moderate, 2.5 years course, experience during travels, with coworkers and wife)

Computer Languages

C, C++, Verilog, VHDL, Forth, 68k assembler, x86 assembler, PIC17 assembler, ARM Cortex-Mx assembler, Lisp/Scheme, Modula-II, Java, Prolog, (La)TeX, HTML, TCL, Perl, Python, bash, Matlab/Simulink

OS (System Programming)

Linux (Debian, OpenSuSE), Windows, (also, but dated: DOS, Atari TOS, HP-UX)


network server dokuwiki, postfix, dovecot, lighttpd, gitlab, mastodon, etc.
RTL synthesis RTL Compiler, Ambit, Design Compiler, Leonardo, Quartus
Simulation NC Sim, Modelsim, Affirma, Spectre, Ultrasim, Hsim, Eldo
Analysis Leda, Formality, Primetime
Design Environment Cadence 5.x, Mentor Graphics
Layout editor Cadence Virtuoso & Encounter, Mentor tools

Development environments

Emacs/Makefiles, MS VC++; Version control systems: bzr, subversion, cvs, git, fossil


These are software projects I own myself or did as free software projects.

Date Project
2011-now net2o: Development of a next generation internet software stack [html] The project involves:
  • a full network stack including cryptography, flow/congestion control and presentation layer on top
  • Modernizing Gforth and the Forth language to be fit for such a task
  • Designing and implementing a GUI framework (called MINOS2) which is fit for the task, fast and portable
  • Operating automatic test and build server with Gitlab EE
  • Building for docker, snap, flatpak, Android, Debian and SuSE
  • Stripped down protocol for embedded CPUs; for that purpose, an IP/UDP stack was developed for Mecrisp on STM32 and similar ARM cores
2014, 2015 Contributions to [html]Cryptech: Rosc-based random number generator, SHA3/Keccak implementation
2012, 2013, 2019 Triceps 2, control a pick&place robot based on three digital servos, play peg solitaire and Go; the robot is operated by a b16 program, the Go playing engine on Android using optical recognition of the game field. This is demo code for LinuxTag, Makerfaire and CCC for the Forth-Gesellschaft booth/assembly
2002, 2004 b16 scalable minimalistic CPU; USB core, see [html]
1997-2011 Development of a GUI editor and a underlying widget library for bigFORTH. bigFORTH port to Linux and Windows, licence change to GPL. About 100 widget classes. Published in Tagungsband Forth Tagung '97, Bernd Paysan, "MINOS - Visual bigFORTH", published on EuroForth'97, find the paper in [html]
1994-1997 Design and implementation of a stack-based VLIW processor architecture especially suited for signal processing, while having low-latency calls and branches to fit high level language demands. Specifying the instruction set architecture, development of a simulator and demo programs, implementation in 12k lines synthesizable Verilog, performance estimation in 0.35u CMOS: at 300 MHz around 2 GOPS. Implements functional units, FPU, caches, instruction decoding, branch unit, bus interface...
Started to write a compiler prototype (not finished).
Diploma Thesis "Implementation of the 4stack processor using Verilog", [html]
1992-now Development of a portable free Forth system based on a C-coded engine (GNU Forth, Gforth), written with a loosely-knit team over the internet. Published e.g. in EuroFORTH '93 conference proceedings, M. Anton Ertl, "A portable Forth engine", see also [html]
1991-1994 Porting bigFORTH to 386/DOS, other features as above, object oriented extension, text-based GUI library.
1988-1991 Development of a Forth compiler system (bigFORTH) on a 68k platform (Atari ST). Generation of peephole-optimizied code. Integrated development environment, featuring decompiler, debugger, assembler, disassembler, support of host OS GUI. Published in VD 3/1991, Bernd Paysan, "Ein optimierender Forth-Compiler" Runs standalone on a 68k VME box, too.

US Patents

These patents were result of my diploma thesis. In my own opinion, they shouldn't have been granted.

Pat. No. Title
6,125,381 Recursively partitioned carry select adder
5,918,075 Access network for addressing subwords in memory for both little and big endian byte order


Sports Cycling, hiking, snorkling, nordic skiing
Books Fantasy like [html]Terry Pratchett, Harry Potter, [htm]Journey to the West
Traveling Great landscape, e.g. in east Asia
Art Painting, photographing, writing satires

Look here for more details [html]

Club Activities

2002-now Director of the [html]Forth-Gesellschaft e.V.
2017-now Tresurer of the [html]Forth-200x standard team


ASIC-Design: My main interest goes to the digital side of mixed-signal design, especially in connection with signal processing, with emphasis on a hardware-software codesign.

Software development: I'm interested in cryptography, networking, user interface libraries and the programming language Forth.

I can think for myself, and as a consequence come up with new and different solutions. Cost and time to market are as important for me as technical excellence. Work on intellectually rewarding projects is an important motivation for me as are trust and responsibility. I see teamwork not just as dividing work up between people, but as room for open discussion, being a consultant and consulting others when necessary.

Created 30dec1997. Last modified: 31jul2023 by MailBernd Paysan